--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: L.68
--  \   \         Application: netgen
--  /   /         Filename: proc_alu_netlist.vhd
-- /___/   /\     Timestamp: Fri May 06 17:07:44 2011
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -w -sim -ofmt vhdl -dir sources sources/proc_alu_netlist.ngc 
-- Device	: xc3s250e-4-tq144
-- Input file	: sources/proc_alu_netlist.ngc
-- Output file	: E:\export\src\netlist\sources\proc_alu_netlist.vhd
-- # of Entities	: 1
-- Design Name	: proc_alu_netlist
-- Xilinx	: c:\Xilinx\11.1\ISE;C:\Xilinx\11.1\EDK
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity proc_alu_netlist is
  port (
    clk : in STD_LOGIC := 'X'; 
    en : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    result : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    status_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    mode : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    a : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    b : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    status_in : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end proc_alu_netlist;

architecture STRUCTURE of proc_alu_netlist is
  signal N10 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N30 : STD_LOGIC; 
  signal N32 : STD_LOGIC; 
  signal N34 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N38 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal N42 : STD_LOGIC; 
  signal N44 : STD_LOGIC; 
  signal N46 : STD_LOGIC; 
  signal N47 : STD_LOGIC; 
  signal N48 : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal N50 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal N52 : STD_LOGIC; 
  signal N53 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal N55 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal N57 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal N59 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal N60 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal N62 : STD_LOGIC; 
  signal alu_N11 : STD_LOGIC; 
  signal alu_N13 : STD_LOGIC; 
  signal alu_N16 : STD_LOGIC; 
  signal alu_N18 : STD_LOGIC; 
  signal alu_N3 : STD_LOGIC; 
  signal alu_N45 : STD_LOGIC; 
  signal alu_c_mod_mux0001_62 : STD_LOGIC; 
  signal alu_s_result_0_43_72 : STD_LOGIC; 
  signal alu_s_result_0_93 : STD_LOGIC; 
  signal alu_s_result_1_14_75 : STD_LOGIC; 
  signal alu_s_result_1_27_76 : STD_LOGIC; 
  signal alu_s_result_1_47_77 : STD_LOGIC; 
  signal alu_s_result_1_6_78 : STD_LOGIC; 
  signal alu_s_result_1_64_79 : STD_LOGIC; 
  signal alu_s_result_2_14_81 : STD_LOGIC; 
  signal alu_s_result_2_27_82 : STD_LOGIC; 
  signal alu_s_result_2_47_83 : STD_LOGIC; 
  signal alu_s_result_2_6_84 : STD_LOGIC; 
  signal alu_s_result_2_64_85 : STD_LOGIC; 
  signal alu_s_result_3_14_87 : STD_LOGIC; 
  signal alu_s_result_3_27_88 : STD_LOGIC; 
  signal alu_s_result_3_47_89 : STD_LOGIC; 
  signal alu_s_result_3_6_90 : STD_LOGIC; 
  signal alu_s_result_3_64_91 : STD_LOGIC; 
  signal alu_s_result_4_14_93 : STD_LOGIC; 
  signal alu_s_result_4_27_94 : STD_LOGIC; 
  signal alu_s_result_4_47_95 : STD_LOGIC; 
  signal alu_s_result_4_6_96 : STD_LOGIC; 
  signal alu_s_result_4_64_97 : STD_LOGIC; 
  signal alu_s_result_5_14_99 : STD_LOGIC; 
  signal alu_s_result_5_27_100 : STD_LOGIC; 
  signal alu_s_result_5_47_101 : STD_LOGIC; 
  signal alu_s_result_5_6_102 : STD_LOGIC; 
  signal alu_s_result_5_64_103 : STD_LOGIC; 
  signal alu_s_result_6_14_105 : STD_LOGIC; 
  signal alu_s_result_6_27_106 : STD_LOGIC; 
  signal alu_s_result_6_47_107 : STD_LOGIC; 
  signal alu_s_result_6_6_108 : STD_LOGIC; 
  signal alu_s_result_6_64_109 : STD_LOGIC; 
  signal alu_s_result_7_6_111 : STD_LOGIC; 
  signal alu_s_result_7_60_112 : STD_LOGIC; 
  signal alu_s_status_out_0_Q : STD_LOGIC; 
  signal alu_s_status_out_1_Q : STD_LOGIC; 
  signal alu_s_status_out_2_Q : STD_LOGIC; 
  signal alu_s_status_out_3_Q : STD_LOGIC; 
  signal alu_s_status_out_5_Q : STD_LOGIC; 
  signal alu_s_status_out_0_mux000014_118 : STD_LOGIC; 
  signal alu_s_status_out_0_mux000022_119 : STD_LOGIC; 
  signal alu_s_status_out_0_mux00004_120 : STD_LOGIC; 
  signal alu_s_status_out_0_mux00005 : STD_LOGIC; 
  signal alu_s_status_out_1_mux0000 : STD_LOGIC; 
  signal alu_s_status_out_1_mux00001_123 : STD_LOGIC; 
  signal alu_s_status_out_2_cmp_eq000028_SW0 : STD_LOGIC; 
  signal alu_s_status_out_5_mux000026_125 : STD_LOGIC; 
  signal alu_s_status_out_5_mux000045_126 : STD_LOGIC; 
  signal alu_status_out_0_Q : STD_LOGIC; 
  signal alu_status_out_1_Q : STD_LOGIC; 
  signal alu_status_out_2_Q : STD_LOGIC; 
  signal alu_status_out_3_Q : STD_LOGIC; 
  signal alu_status_out_5_Q : STD_LOGIC; 
  signal alu_Madd_temp_sum_add0000_cy : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal alu_Madd_temp_sum_add0000_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal alu_result : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal NlwRenamedSignal_alu_result : STD_LOGIC_VECTOR ( 7 downto 7 ); 
  signal alu_s_result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal alu_status_operation : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal alu_temp_sum_add0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSignal_status_out : STD_LOGIC_VECTOR ( 6 downto 6 ); 
begin
  result(7) <= NlwRenamedSignal_alu_result(7);
  result(6) <= alu_result(6);
  result(5) <= alu_result(5);
  result(4) <= alu_result(4);
  result(3) <= alu_result(3);
  result(2) <= alu_result(2);
  result(1) <= alu_result(1);
  result(0) <= alu_result(0);
  status_out(7) <= NlwRenamedSignal_status_out(6);
  status_out(6) <= NlwRenamedSignal_status_out(6);
  status_out(5) <= alu_status_out_5_Q;
  status_out(4) <= NlwRenamedSignal_alu_result(7);
  status_out(3) <= alu_status_out_3_Q;
  status_out(2) <= alu_status_out_2_Q;
  status_out(1) <= alu_status_out_1_Q;
  status_out(0) <= alu_status_out_0_Q;
  XST_GND : GND
    port map (
      G => NlwRenamedSignal_status_out(6)
    );
  alu_Madd_temp_sum_add0000_xor_7_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(6),
      LI => alu_Madd_temp_sum_add0000_lut(7),
      O => alu_temp_sum_add0000(7)
    );
  alu_Madd_temp_sum_add0000_cy_7_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(6),
      DI => a(7),
      S => alu_Madd_temp_sum_add0000_lut(7),
      O => alu_Madd_temp_sum_add0000_cy(7)
    );
  alu_Madd_temp_sum_add0000_xor_6_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(5),
      LI => alu_Madd_temp_sum_add0000_lut(6),
      O => alu_temp_sum_add0000(6)
    );
  alu_Madd_temp_sum_add0000_cy_6_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(5),
      DI => a(6),
      S => alu_Madd_temp_sum_add0000_lut(6),
      O => alu_Madd_temp_sum_add0000_cy(6)
    );
  alu_Madd_temp_sum_add0000_xor_5_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(4),
      LI => alu_Madd_temp_sum_add0000_lut(5),
      O => alu_temp_sum_add0000(5)
    );
  alu_Madd_temp_sum_add0000_cy_5_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(4),
      DI => a(5),
      S => alu_Madd_temp_sum_add0000_lut(5),
      O => alu_Madd_temp_sum_add0000_cy(5)
    );
  alu_Madd_temp_sum_add0000_xor_4_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(3),
      LI => alu_Madd_temp_sum_add0000_lut(4),
      O => alu_temp_sum_add0000(4)
    );
  alu_Madd_temp_sum_add0000_cy_4_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(3),
      DI => a(4),
      S => alu_Madd_temp_sum_add0000_lut(4),
      O => alu_Madd_temp_sum_add0000_cy(4)
    );
  alu_Madd_temp_sum_add0000_xor_3_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(2),
      LI => alu_Madd_temp_sum_add0000_lut(3),
      O => alu_temp_sum_add0000(3)
    );
  alu_Madd_temp_sum_add0000_cy_3_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(2),
      DI => a(3),
      S => alu_Madd_temp_sum_add0000_lut(3),
      O => alu_Madd_temp_sum_add0000_cy(3)
    );
  alu_Madd_temp_sum_add0000_xor_2_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(1),
      LI => alu_Madd_temp_sum_add0000_lut(2),
      O => alu_temp_sum_add0000(2)
    );
  alu_Madd_temp_sum_add0000_cy_2_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(1),
      DI => a(2),
      S => alu_Madd_temp_sum_add0000_lut(2),
      O => alu_Madd_temp_sum_add0000_cy(2)
    );
  alu_Madd_temp_sum_add0000_xor_1_Q : XORCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(0),
      LI => alu_Madd_temp_sum_add0000_lut(1),
      O => alu_temp_sum_add0000(1)
    );
  alu_Madd_temp_sum_add0000_cy_1_Q : MUXCY
    port map (
      CI => alu_Madd_temp_sum_add0000_cy(0),
      DI => a(1),
      S => alu_Madd_temp_sum_add0000_lut(1),
      O => alu_Madd_temp_sum_add0000_cy(1)
    );
  alu_Madd_temp_sum_add0000_xor_0_Q : XORCY
    port map (
      CI => alu_c_mod_mux0001_62,
      LI => alu_Madd_temp_sum_add0000_lut(0),
      O => alu_temp_sum_add0000(0)
    );
  alu_Madd_temp_sum_add0000_cy_0_Q : MUXCY
    port map (
      CI => alu_c_mod_mux0001_62,
      DI => a(0),
      S => alu_Madd_temp_sum_add0000_lut(0),
      O => alu_Madd_temp_sum_add0000_cy(0)
    );
  alu_status_out_5 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_status_out_5_Q,
      R => rst,
      Q => alu_status_out_5_Q
    );
  alu_status_out_3 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_status_out_3_Q,
      R => rst,
      Q => alu_status_out_3_Q
    );
  alu_status_out_2 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_status_out_2_Q,
      R => rst,
      Q => alu_status_out_2_Q
    );
  alu_status_out_1 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_status_out_1_Q,
      R => rst,
      Q => alu_status_out_1_Q
    );
  alu_status_out_0 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_status_out_0_Q,
      R => rst,
      Q => alu_status_out_0_Q
    );
  alu_result_7 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(7),
      R => rst,
      Q => NlwRenamedSignal_alu_result(7)
    );
  alu_result_6 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(6),
      R => rst,
      Q => alu_result(6)
    );
  alu_result_5 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(5),
      R => rst,
      Q => alu_result(5)
    );
  alu_result_4 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(4),
      R => rst,
      Q => alu_result(4)
    );
  alu_result_3 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(3),
      R => rst,
      Q => alu_result(3)
    );
  alu_result_2 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(2),
      R => rst,
      Q => alu_result(2)
    );
  alu_result_1 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(1),
      R => rst,
      Q => alu_result(1)
    );
  alu_result_0 : FDRE
    port map (
      C => clk,
      CE => en,
      D => alu_s_result(0),
      R => rst,
      Q => alu_result(0)
    );
  alu_s_status_out_1_mux00001 : LUT4
    generic map(
      INIT => X"F4D4"
    )
    port map (
      I0 => alu_temp_sum_add0000(3),
      I1 => b(3),
      I2 => a(3),
      I3 => alu_status_operation(2),
      O => alu_s_status_out_1_mux0000
    );
  alu_s_status_out_1_mux00002 : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => alu_status_operation(2),
      I1 => status_in(1),
      I2 => a(3),
      O => alu_s_status_out_1_mux00001_123
    );
  alu_s_status_out_1_mux0000_f5 : MUXF5
    port map (
      I0 => alu_s_status_out_1_mux00001_123,
      I1 => alu_s_status_out_1_mux0000,
      S => alu_status_operation(1),
      O => alu_s_status_out_1_Q
    );
  alu_s_result_0_52 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => status_in(0),
      I1 => mode(3),
      I2 => mode(2),
      I3 => mode(1),
      O => alu_N45
    );
  alu_s_result_3_47 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => a(3),
      I1 => alu_N13,
      I2 => b(3),
      I3 => alu_N18,
      O => alu_s_result_3_47_89
    );
  alu_s_result_3_64 : LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => alu_s_status_out_0_mux00005,
      I1 => alu_s_result_3_14_87,
      I2 => alu_s_result_3_27_88,
      I3 => alu_s_result_3_47_89,
      O => alu_s_result_3_64_91
    );
  alu_s_result_3_90 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_3_6_90,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(3),
      I3 => alu_s_result_3_64_91,
      O => alu_s_result(3)
    );
  alu_s_result_2_47 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => a(2),
      I1 => alu_N13,
      I2 => b(2),
      I3 => alu_N18,
      O => alu_s_result_2_47_83
    );
  alu_s_result_2_64 : LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => alu_s_status_out_0_mux00005,
      I1 => alu_s_result_2_14_81,
      I2 => alu_s_result_2_27_82,
      I3 => alu_s_result_2_47_83,
      O => alu_s_result_2_64_85
    );
  alu_s_result_2_90 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_2_6_84,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(2),
      I3 => alu_s_result_2_64_85,
      O => alu_s_result(2)
    );
  alu_s_result_1_47 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => a(1),
      I1 => alu_N13,
      I2 => b(1),
      I3 => alu_N18,
      O => alu_s_result_1_47_77
    );
  alu_s_result_1_64 : LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => alu_s_status_out_0_mux00005,
      I1 => alu_s_result_1_14_75,
      I2 => alu_s_result_1_27_76,
      I3 => alu_s_result_1_47_77,
      O => alu_s_result_1_64_79
    );
  alu_s_result_1_90 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_1_6_78,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(1),
      I3 => alu_s_result_1_64_79,
      O => alu_s_result(1)
    );
  alu_s_result_4_47 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => a(4),
      I1 => alu_N13,
      I2 => b(4),
      I3 => alu_N18,
      O => alu_s_result_4_47_95
    );
  alu_s_result_4_64 : LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => alu_s_status_out_0_mux00005,
      I1 => alu_s_result_4_14_93,
      I2 => alu_s_result_4_27_94,
      I3 => alu_s_result_4_47_95,
      O => alu_s_result_4_64_97
    );
  alu_s_result_4_90 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_4_6_96,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(4),
      I3 => alu_s_result_4_64_97,
      O => alu_s_result(4)
    );
  alu_s_result_5_47 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => a(5),
      I1 => alu_N13,
      I2 => b(5),
      I3 => alu_N18,
      O => alu_s_result_5_47_101
    );
  alu_s_result_5_64 : LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => alu_s_status_out_0_mux00005,
      I1 => alu_s_result_5_14_99,
      I2 => alu_s_result_5_27_100,
      I3 => alu_s_result_5_47_101,
      O => alu_s_result_5_64_103
    );
  alu_s_result_5_90 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_5_6_102,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(5),
      I3 => alu_s_result_5_64_103,
      O => alu_s_result(5)
    );
  alu_s_result_6_47 : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => a(6),
      I1 => alu_N13,
      I2 => b(6),
      I3 => alu_N18,
      O => alu_s_result_6_47_107
    );
  alu_s_result_6_64 : LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      I0 => alu_s_status_out_0_mux00005,
      I1 => alu_s_result_6_14_105,
      I2 => alu_s_result_6_27_106,
      I3 => alu_s_result_6_47_107,
      O => alu_s_result_6_64_109
    );
  alu_s_result_6_90 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_6_6_108,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(6),
      I3 => alu_s_result_6_64_109,
      O => alu_s_result(6)
    );
  alu_c_mod_mux0001_SW0 : LUT4
    generic map(
      INIT => X"D9D3"
    )
    port map (
      I0 => mode(2),
      I1 => mode(1),
      I2 => mode(0),
      I3 => status_in(0),
      O => N2
    );
  alu_c_mod_mux0001 : LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => mode(3),
      I1 => N2,
      O => alu_c_mod_mux0001_62
    );
  alu_s_result_0_48 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => en,
      I1 => mode(0),
      O => alu_s_status_out_0_mux00005
    );
  alu_s_result_0_131 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => mode(2),
      I1 => mode(1),
      I2 => mode(3),
      O => alu_N18
    );
  alu_s_result_1_410 : LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      I0 => mode(3),
      I1 => en,
      I2 => alu_N3,
      I3 => mode(0),
      O => alu_status_operation(2)
    );
  alu_s_result_0_31_SW0 : LUT3
    generic map(
      INIT => X"91"
    )
    port map (
      I0 => mode(2),
      I1 => mode(1),
      I2 => mode(0),
      O => N4
    );
  alu_s_result_0_31 : LUT3
    generic map(
      INIT => X"10"
    )
    port map (
      I0 => mode(3),
      I1 => N4,
      I2 => en,
      O => alu_status_operation(1)
    );
  alu_s_status_out_0_mux00004 : LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      I0 => alu_status_operation(3),
      I1 => a(0),
      I2 => alu_status_operation(2),
      I3 => a(7),
      O => alu_s_status_out_0_mux00004_120
    );
  alu_s_status_out_0_mux000043 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_status_out_0_mux00004_120,
      I1 => alu_status_operation(1),
      I2 => alu_Madd_temp_sum_add0000_cy(7),
      I3 => alu_s_status_out_0_mux000022_119,
      O => alu_s_status_out_0_Q
    );
  alu_s_result_1_21 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => mode(1),
      I1 => mode(2),
      O => alu_N3
    );
  alu_b_mod_mux0001_0_21 : LUT4
    generic map(
      INIT => X"0220"
    )
    port map (
      I0 => mode(2),
      I1 => mode(3),
      I2 => mode(0),
      I3 => mode(1),
      O => alu_N16
    );
  alu_b_mod_mux0001_0_11 : LUT4
    generic map(
      INIT => X"FF9B"
    )
    port map (
      I0 => mode(0),
      I1 => mode(1),
      I2 => mode(2),
      I3 => mode(3),
      O => alu_N11
    );
  alu_s_status_out_5_mux000026 : LUT4
    generic map(
      INIT => X"2008"
    )
    port map (
      I0 => alu_status_operation(1),
      I1 => alu_s_result(7),
      I2 => a(7),
      I3 => b(7),
      O => alu_s_status_out_5_mux000026_125
    );
  alu_s_status_out_5_mux000045 : LUT4
    generic map(
      INIT => X"3C28"
    )
    port map (
      I0 => alu_status_operation(2),
      I1 => alu_s_result(7),
      I2 => alu_s_status_out_0_Q,
      I3 => alu_status_operation(3),
      O => alu_s_status_out_5_mux000045_126
    );
  alu_s_status_out_5_mux000046 : LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      I0 => alu_s_status_out_5_mux000026_125,
      I1 => alu_s_status_out_5_mux000045_126,
      O => alu_s_status_out_5_Q
    );
  alu_s_result_7_88 : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_7_6_111,
      I1 => alu_status_operation(1),
      I2 => alu_temp_sum_add0000(7),
      I3 => alu_s_result_7_60_112,
      O => alu_s_result(7)
    );
  alu_s_status_out_2_cmp_eq000028 : LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      I0 => alu_s_result(0),
      I1 => alu_s_result(1),
      I2 => alu_s_result(2),
      I3 => N6,
      O => alu_s_status_out_2_Q
    );
  alu_s_result_0_65_SW0 : LUT4
    generic map(
      INIT => X"EE20"
    )
    port map (
      I0 => a(0),
      I1 => b(0),
      I2 => alu_N13,
      I3 => alu_N18,
      O => N10
    );
  alu_Madd_temp_sum_add0000_lut_7_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(7),
      I1 => b(7),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(7)
    );
  alu_Madd_temp_sum_add0000_lut_6_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(6),
      I1 => b(6),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(6)
    );
  alu_Madd_temp_sum_add0000_lut_5_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(5),
      I1 => b(5),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(5)
    );
  alu_Madd_temp_sum_add0000_lut_4_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(4),
      I1 => b(4),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(4)
    );
  alu_Madd_temp_sum_add0000_lut_3_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(3),
      I1 => b(3),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(3)
    );
  alu_Madd_temp_sum_add0000_lut_2_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(2),
      I1 => b(2),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(2)
    );
  alu_Madd_temp_sum_add0000_lut_1_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(1),
      I1 => b(1),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(1)
    );
  alu_Madd_temp_sum_add0000_lut_0_Q : LUT4
    generic map(
      INIT => X"569A"
    )
    port map (
      I0 => a(0),
      I1 => b(0),
      I2 => alu_N16,
      I3 => alu_N11,
      O => alu_Madd_temp_sum_add0000_lut(0)
    );
  alu_s_result_0_43 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(0),
      I2 => mode(3),
      I3 => b(0),
      O => alu_s_result_0_43_72
    );
  alu_s_result_3_27 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(3),
      I2 => mode(3),
      I3 => b(3),
      O => alu_s_result_3_27_88
    );
  alu_s_result_2_27 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(2),
      I2 => mode(3),
      I3 => b(2),
      O => alu_s_result_2_27_82
    );
  alu_s_result_1_27 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(1),
      I2 => mode(3),
      I3 => b(1),
      O => alu_s_result_1_27_76
    );
  alu_s_result_4_27 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(4),
      I2 => mode(3),
      I3 => b(4),
      O => alu_s_result_4_27_94
    );
  alu_s_result_5_27 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(5),
      I2 => mode(3),
      I3 => b(5),
      O => alu_s_result_5_27_100
    );
  alu_s_result_6_27 : LUT4
    generic map(
      INIT => X"1101"
    )
    port map (
      I0 => alu_N3,
      I1 => a(6),
      I2 => mode(3),
      I3 => b(6),
      O => alu_s_result_6_27_106
    );
  alu_s_result_3_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(3),
      I2 => mode(0),
      I3 => en,
      O => N24
    );
  alu_s_result_3_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(3),
      I1 => N24,
      I2 => alu_status_operation(2),
      I3 => a(2),
      O => alu_s_result_3_6_90
    );
  alu_s_result_2_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(2),
      I2 => mode(0),
      I3 => en,
      O => N26
    );
  alu_s_result_2_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(2),
      I1 => N26,
      I2 => alu_status_operation(2),
      I3 => a(1),
      O => alu_s_result_2_6_84
    );
  alu_s_result_1_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(1),
      I2 => mode(0),
      I3 => en,
      O => N28
    );
  alu_s_result_1_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(1),
      I1 => N28,
      I2 => alu_status_operation(2),
      I3 => a(0),
      O => alu_s_result_1_6_78
    );
  alu_s_result_4_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(4),
      I2 => mode(0),
      I3 => en,
      O => N30
    );
  alu_s_result_4_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(4),
      I1 => N30,
      I2 => alu_status_operation(2),
      I3 => a(3),
      O => alu_s_result_4_6_96
    );
  alu_s_result_5_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(5),
      I2 => mode(0),
      I3 => en,
      O => N32
    );
  alu_s_result_5_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(5),
      I1 => N32,
      I2 => alu_status_operation(2),
      I3 => a(4),
      O => alu_s_result_5_6_102
    );
  alu_s_result_6_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(6),
      I2 => mode(0),
      I3 => en,
      O => N34
    );
  alu_s_result_6_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(6),
      I1 => N34,
      I2 => alu_status_operation(2),
      I3 => a(5),
      O => alu_s_result_6_6_108
    );
  alu_status_operation_3_1 : LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      I0 => en,
      I1 => mode(0),
      I2 => alu_N3,
      I3 => mode(3),
      O => alu_status_operation(3)
    );
  alu_s_status_out_0_mux000014 : LUT4
    generic map(
      INIT => X"5545"
    )
    port map (
      I0 => alu_status_operation(3),
      I1 => N4,
      I2 => en,
      I3 => mode(3),
      O => alu_s_status_out_0_mux000014_118
    );
  alu_s_status_out_0_mux000022_SW0 : LUT4
    generic map(
      INIT => X"FFF7"
    )
    port map (
      I0 => en,
      I1 => mode(0),
      I2 => alu_N3,
      I3 => mode(3),
      O => N36
    );
  alu_s_status_out_0_mux000022 : LUT4
    generic map(
      INIT => X"20FF"
    )
    port map (
      I0 => status_in(0),
      I1 => alu_status_operation(2),
      I2 => alu_s_status_out_0_mux000014_118,
      I3 => N36,
      O => alu_s_status_out_0_mux000022_119
    );
  alu_s_result_0_111 : LUT3
    generic map(
      INIT => X"10"
    )
    port map (
      I0 => mode(1),
      I1 => mode(2),
      I2 => mode(3),
      O => alu_N13
    );
  alu_Mxor_s_status_out_3_Result1 : LUT3
    generic map(
      INIT => X"36"
    )
    port map (
      I0 => alu_s_status_out_5_mux000045_126,
      I1 => alu_s_result(7),
      I2 => alu_s_status_out_5_mux000026_125,
      O => alu_s_status_out_3_Q
    );
  alu_s_result_7_6_SW0 : LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      I0 => alu_N13,
      I1 => b(7),
      I2 => mode(0),
      I3 => en,
      O => N38
    );
  alu_s_result_7_6 : LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      I0 => a(7),
      I1 => N38,
      I2 => alu_status_operation(2),
      I3 => a(6),
      O => alu_s_result_7_6_111
    );
  alu_s_result_7_60 : LUT4
    generic map(
      INIT => X"8880"
    )
    port map (
      I0 => en,
      I1 => mode(0),
      I2 => alu_N45,
      I3 => N40,
      O => alu_s_result_7_60_112
    );
  alu_s_result_0_65_SW1 : LUT3
    generic map(
      INIT => X"A8"
    )
    port map (
      I0 => mode(3),
      I1 => mode(1),
      I2 => mode(2),
      O => N44
    );
  alu_s_result_3_14 : MUXF5
    port map (
      I0 => N46,
      I1 => N47,
      S => mode(1),
      O => alu_s_result_3_14_87
    );
  alu_s_result_3_14_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => mode(3),
      I1 => a(4),
      I2 => mode(2),
      O => N46
    );
  alu_s_result_3_14_G : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => mode(3),
      I1 => a(4),
      I2 => b(3),
      I3 => mode(2),
      O => N47
    );
  alu_s_result_2_14 : MUXF5
    port map (
      I0 => N48,
      I1 => N49,
      S => mode(1),
      O => alu_s_result_2_14_81
    );
  alu_s_result_2_14_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => mode(3),
      I1 => a(3),
      I2 => mode(2),
      O => N48
    );
  alu_s_result_2_14_G : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => mode(3),
      I1 => a(3),
      I2 => b(2),
      I3 => mode(2),
      O => N49
    );
  alu_s_result_1_14 : MUXF5
    port map (
      I0 => N50,
      I1 => N51,
      S => mode(1),
      O => alu_s_result_1_14_75
    );
  alu_s_result_1_14_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => mode(3),
      I1 => a(2),
      I2 => mode(2),
      O => N50
    );
  alu_s_result_1_14_G : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => mode(3),
      I1 => a(2),
      I2 => b(1),
      I3 => mode(2),
      O => N51
    );
  alu_s_result_4_14 : MUXF5
    port map (
      I0 => N52,
      I1 => N53,
      S => mode(1),
      O => alu_s_result_4_14_93
    );
  alu_s_result_4_14_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => mode(3),
      I1 => a(5),
      I2 => mode(2),
      O => N52
    );
  alu_s_result_4_14_G : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => mode(3),
      I1 => a(5),
      I2 => b(4),
      I3 => mode(2),
      O => N53
    );
  alu_s_result_5_14 : MUXF5
    port map (
      I0 => N54,
      I1 => N55,
      S => mode(1),
      O => alu_s_result_5_14_99
    );
  alu_s_result_5_14_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => mode(3),
      I1 => a(6),
      I2 => mode(2),
      O => N54
    );
  alu_s_result_5_14_G : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => mode(3),
      I1 => a(6),
      I2 => b(5),
      I3 => mode(2),
      O => N55
    );
  alu_s_result_6_14 : MUXF5
    port map (
      I0 => N56,
      I1 => N57,
      S => mode(1),
      O => alu_s_result_6_14_105
    );
  alu_s_result_6_14_F : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => mode(3),
      I1 => a(7),
      I2 => mode(2),
      O => N56
    );
  alu_s_result_6_14_G : LUT4
    generic map(
      INIT => X"D888"
    )
    port map (
      I0 => mode(3),
      I1 => a(7),
      I2 => b(6),
      I3 => mode(2),
      O => N57
    );
  alu_s_result_7_60_SW0 : MUXF5
    port map (
      I0 => N58,
      I1 => N59,
      S => mode(2),
      O => N40
    );
  alu_s_result_7_60_SW0_F : LUT4
    generic map(
      INIT => X"1211"
    )
    port map (
      I0 => a(7),
      I1 => mode(1),
      I2 => b(7),
      I3 => mode(3),
      O => N58
    );
  alu_s_result_7_60_SW0_G : LUT4
    generic map(
      INIT => X"AA08"
    )
    port map (
      I0 => mode(1),
      I1 => b(7),
      I2 => mode(3),
      I3 => a(7),
      O => N59
    );
  alu_s_result_0_93_SW0 : MUXF5
    port map (
      I0 => N60,
      I1 => N61,
      S => mode(0),
      O => N42
    );
  alu_s_result_0_93_SW0_F : LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      I0 => a(0),
      I1 => alu_N13,
      I2 => b(0),
      I3 => alu_N45,
      O => N60
    );
  alu_s_result_0_93_SW0_G : LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      I0 => alu_s_result_0_43_72,
      I1 => a(1),
      I2 => N44,
      I3 => N10,
      O => N61
    );
  XST_VCC : VCC
    port map (
      P => N62
    );
  alu_s_status_out_2_cmp_eq000028_SW01 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => alu_s_result(6),
      I1 => alu_s_result(5),
      I2 => alu_s_result(4),
      I3 => alu_s_result(3),
      O => alu_s_status_out_2_cmp_eq000028_SW0
    );
  alu_s_status_out_2_cmp_eq000028_SW0_f5 : MUXF5
    port map (
      I0 => alu_s_status_out_2_cmp_eq000028_SW0,
      I1 => N62,
      S => alu_s_result(7),
      O => N6
    );
  alu_s_result_0_931 : LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      I0 => mode(3),
      I1 => N4,
      I2 => en,
      I3 => alu_temp_sum_add0000(0),
      O => alu_s_result_0_93
    );
  alu_s_result_0_93_f5 : MUXF5
    port map (
      I0 => alu_s_result_0_93,
      I1 => en,
      S => N42,
      O => alu_s_result(0)
    );

end STRUCTURE;

